Patent · US Expired

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

US6982451B1 · kind B1 · utility

13Cited by

4References

12Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Martin L. Voogel · Los Altos, US
Austin H. Lesea · Los Gatos, US
Joseph J. Fabula · Tucson, US
Carl H. Carmichael · San Jose, US
Shahin Toutounchi · Pleasanton, US
Michael J. Hart · Palo Alto, US
Steven P. Young · Boulder, US
Kevin T. Look · Fremont, US
Jan Lodewijk de Jong · Cupertino, US

Key dates

Filing date	Mar 27, 2003
Grant date	Jan 3, 2006
Priority date	—
Expiry date	Oct 25, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH10B10/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.