Deterministic bist architecture including MISR filter
US6993694B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2002 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Sep 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.