Redundant memory structure using bad bit pointers
US6996017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Oct 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.