Hazard queue for transaction pipeline
US6996665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Mar 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.