Method for fabricating a storage capacitor
US6998307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.