MOSFET structure with high mechanical stress in the channel
US7002209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.