Split gate flash memory cell
US7005698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | May 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.