Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency
US7010652B2 · kind B2 · utility
116Cited by
11References
12Claims
0Family size
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Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Aug 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.