Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches
US7015090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2003 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | May 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.