Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate

US7015095B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mathias Krause · Spenge, DE
• Christoph Ludwig · Radeberg, DE
• Jens-Uwe Sachse · Dresden, DE
• Joachim Deppe · Dresden, DE
• Ralf Richter · Dresden, DE
• Christoph Kleint · Dresden, DE
• Ricardo P. Mikalo · Stadtroda, DE

Key dates

• Filing date: May 27, 2004
• Grant date: Mar 21, 2006
• Expiry date: May 27, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.