Patent · US Expired

Delay locked loop

US7016452B2 · kind B2 · utility

9Cited by

4References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Torsten Partsch · San Jose, US
Thomas Hein · Hersbruck, DE
Thilo Marx · Villingen-Schwenningen, DE
Patrick Heyne · Hersbruck, DE

Key dates

Filing date	Jun 24, 2002
Grant date	Mar 21, 2006
Priority date	—
Expiry date	Aug 2, 2024

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00058
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.