Post high voltage gate oxide pattern high-vacuum outgas surface treatment
US7018925B2 · kind B2 · utility
3Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Feb 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.