Ramped soft programming for control of erase voltage distributions in flash memory devices
US7020021B1 · kind B1 · utility
3Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Nov 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3477
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.