Quad flat flip chip packaging process and leadframe therefor
US7022551B2 · kind B2 · utility
1Cited by
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12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.