Semiconductor component and method for precluding stress-induced void formation in the semiconductor component
US7026225B1 · kind B1 · utility
4Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | May 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.