Method of self-repairing dynamic random access memory
US7028234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Aug 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.