Techniques for patterning features in semiconductor devices
US7030008B2 · kind B2 · utility
9Cited by
9References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.