Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US7031209B2 · kind B2 · utility
26Cited by
95References
21Claims
0Family size
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Key dates
| Filing date | Mar 9, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Oct 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.