Strained transistor architecture and method
US7041543B1 · kind B1 · utility
16Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Aug 20, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is NMOS devices using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in NMOS channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.