Hard substrate wafer sawing process
US7041579B2 · kind B2 · utility
7Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Mar 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.