Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction
US7045428B2 · kind B2 · utility
12Cited by
19References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 26, 2004 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Oct 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.