Method for integrating high-k dielectrics in transistor devices
US7045431B2 · kind B2 · utility
37Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.