Method for forming a low thermal budget spacer
US7049200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | May 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, and striking a second plasma to form a carbon-doped nitride layer on the oxide layer, where the second plasma may be generated from a nitride gas that includes NH3 and the bis-(tertiarybutylamine)silane. The first and second plasmas may be formed using plasma CVD and the bis-(tertiarybutylamine)silane flows uninterrupted between the striking of the first plasma and the striking of the second plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.