Post high voltage gate dielectric pattern plasma surface treatment
US7049242B2 · kind B2 · utility
3Cited by
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21Claims
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Key dates
| Filing date | Jan 6, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Sep 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.