Method for selective fabrication of high capacitance density areas in a low dielectric constant material
US7049246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2000 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | May 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion source. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of interconnect trenches are etched in the first area of the dielectric and a number of capacitor trenches are etched in the second area of the dielectric. The interconnect trenches and the capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.