Heat treatment for edges of multilayer semiconductor wafers
US7049250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes selecting thickness values for the layers of the wafer to provide substantially equivalent heat absorption coefficients both in the central region and the edge of the wafer. This results in a substantially equivalent temperature being attained over the surface of the central region and the peripheral edge during thermal treatment. In turn, that prevents the appearance of slip lines on those surfaces while also preventing deformation of the wafer due to the thermal treatment. To achieve the desired thickness, layers or portions of layers can be selectively added or otherwise provided upon the central region or peripheral edge of the wafer, or on both, to modify the heat absorption coefficient of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.