Patent · US Expired

Charge-trapping memory device including high permittivity strips

US7049651B2 · kind B2 · utility

8Cited by

6References

10Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Mikolajick · Birkenfeld, DE
Hans Reisinger · Grünwald, DE
Josef Willer · Riemerling, DE
Corvin Liaw · Birkenfeld, DE

Key dates

Filing date	Nov 17, 2003
Grant date	May 23, 2006
Priority date	—
Expiry date	Feb 10, 2024

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.