Transistor layout configuration for tight-pitched memory array lines
US7054219B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.