Memory device and method of simultaneous fabrication of core and periphery of same

US7060564B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Inkuk Kang · San Jose, US
• Hiroyuki Kinoshita · San Jose, US
• Weidong Qian · Sunnyvale, US
• Kelwin Ko · San Jose, US
• Yu Sun · Saratoga, US

Key dates

• Filing date: Aug 6, 2003
• Grant date: Jun 13, 2006
• Expiry date: Apr 30, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.