Deep filled vias

US7060624B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Panayotis Andricacos · Ossining, US
• Emanuel I. Cooper · Scarsdale, US
• Timothy J. Dalton · Ridgefield, US
• Hariklia Deligianni · Alpine, US
• Daniel Guidotti · Yorktown Heights, US
• Keith Kwietniak
• Michelle L. Steen · Danbury, US
• Cornelia K. Tsang · Potsdam, US

Key dates

• Filing date: Aug 13, 2003
• Grant date: Jun 13, 2006
• Expiry date: Nov 27, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76898
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via.In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.