Stackable semiconductor package having semiconductor chip within central through hole of substrate
US7061120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | May 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable semiconductor package includes a substrate having a first surface, an opposite second surface, and through hole. Circuit patterns on the first and second surfaces of the substrate include lands, and the circuit patterns of the second surface also include bond fingers. A semiconductor chip is in the throughhole. The semiconductor chip has bond pads, which are oriented in a same direction as the second surface of the substrate. Wires electrically connect the bond pads to the bond fingers. An encapsulant fills the through hole and covers the semiconductor chip, the wires and the bond fingers, without covering the lands. Conductive balls are fused to the lands of the first surface of the substrate. A second semiconductor package may be stacked on the second surface of the substrate, and conductive balls of the second semiconductor package may be fused to the lands of the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.