Stacked die packaging and fabrication method
US7064430B2 · kind B2 · utility
7Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Sep 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least one top die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.