Mask layer and dual damascene interconnect structure in a semiconductor device
US7067419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.