SRAM having an improved capacitor
US7067864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2001 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.