MRAM arrays with reduced bit line resistance and method to make the same
US7071009B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 1, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | May 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved MRAM arrays and a method of forming the same are disclosed in which a bit line has thinner portions formed over MTJs and thicker portions therebetween. Bottom electrodes are formed in a first insulation layer on a substrate and then MTJs and a coplanar second insulation layer are formed thereon. After a second conductive layer comprised of lower metal lines is formed above the MTJs, a trench is formed in a stack of insulation layers above portions of the lower metal lines. A barrier layer and upper metal layer are sequentially deposited and then planarized to form a filled trench that effectively increases a bit line thickness. The lower metal layer is a thin bit line in regions over MTJs. The method may also comprise forming word lines on an insulation layer that are aligned over the MTJs and perpendicular to the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.