Doping of semiconductor fin devices
US7074656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0241
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.