Dual metal gate electrode semiconductor fabrication process and structure thereof

US7074664B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Ted R. White · Austin, US
• Olubunmi O. Adetutu · Austin, US
• Robert E. Jones · Austin, US

Key dates

• Filing date: Mar 29, 2005
• Grant date: Jul 11, 2006
• Expiry date: Mar 29, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.