Memory with improved charge-trapping dielectric layer
US7074677B1 · kind B1 · utility
1Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2002 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.