Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells

US7075148B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Hofmann · Munich, DE
• Erhard Landgraf · Dresden, DE
• Richard Luyken · Munich, DE
• Thomas Schulz · Austin, US
• Michael Specht · Munich, DE

Key dates

• Filing date: Mar 5, 2005
• Grant date: Jul 11, 2006
• Expiry date: Mar 5, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.