Methods and apparatus for implementing a power down in a memory device
US7079441B1 · kind B1 · utility
77Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Feb 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.