Methods of fabricating a semiconductor device having MOS transistor with strained channel
US7084061B2 · kind B2 · utility
18Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.