Use of Ta-capped metal line to improve formation of memory element films
US7084062B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.