Nonvolatile integrated semiconductor memory

US7084454B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Cay-Uwe Pinnow · Birkenfeld, DE
• Martin Gutsche · Dorfen, DE
• Harald Seidl · Brandenburg an der Havel, DE
• Thomas Happ · Tarrytown, US

Key dates

• Filing date: Sep 28, 2004
• Grant date: Aug 1, 2006
• Expiry date: Sep 29, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.