TEOS assisted oxide CMP process
US7091103B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.