Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor
US7098676B2 · kind B2 · utility
38Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Nov 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.