Ashable layers for reducing critical dimensions of integrated circuit features

US7105442B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Hongching Shan · San Jose, US
• Kenny L. Doan · San Jose, US
• Jingbao Liu · Sunnyvale, US
• Michael Barnes · San Ramon, US
• Hong Dang Nguyen · San Jose, US
• Christopher Dennis Bencher · San Jose, US
• Christopher S. Ngai · Burlingame, US
• Wendy H. Yeh · Mountain View, US
• Eda Tuncel · Menlo Park, US
• Claes Bjorkman · Mountain View, US

Key dates

• Filing date: May 22, 2002
• Grant date: Sep 12, 2006
• Expiry date: May 22, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31116
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.