Test device, test system and method for testing a memory circuit

US7107501B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Carsten Ohlhoff · Hersbruck, DE
• Peter Beer · Waldshut-Tiengen, DE

Key dates

• Filing date: Jun 2, 2003
• Grant date: Sep 12, 2006
• Expiry date: Jul 15, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/5606
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.