Through-substrate interconnect fabrication methods
US7109068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2005 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | May 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on both sides of the substrate, (b) forming a precursor aperture in the substrate at a desired location by laser or etch, (c) further etching the precursor aperture to enlarge and shape at least a portion thereof with undercut portions below an initial etch mask layer, (d) lining the aperture with a passivation material, (e) filling the aperture with a conductive material, and (f) thinning one or both surfaces of the substrate to achieve desired stand-off distances of the opposed via ends. The shaped via aperture has an enlarged central portion, and one or more end portions which taper to smaller end surfaces. The one or more via end portions may be trapezoidal in shape. A further rounding etch act following the shaping etch will result in a rounded, i.e., frustoconical, shape. The shape is conducive to improved solder ball/bump attachment, and enables forming vias of very small diameter and pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.