Method for measuring gate dielectric properties for three dimensional transistors
US7109735B1 · kind B1 · utility
1Cited by
6References
16Claims
0Family size
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Key dates
| Filing date | Aug 2, 2005 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Aug 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2648
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for measuring three-dimensional gate dielectric structures can involve forming test patterns that cover a range of dimensional values for the fins on which the gate dielectric structures are formed. Then, by measuring the gate dielectric properties and then correlating those measurements with the underlying fin dimensions, a relationship between fin dimension(s) and gate dielectric properties can be determined. That relationship can then be applied to actual device structures to interpolate/extrapolate gate dielectric property values based on the fin dimensions in the actual device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.