Stepped tip junction with spacer layer

US7112859B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ibrahim Ban · Beaverton, US
• Bernhard Sell · Dresden, DE
• Sanjay Natarajan · Portland, US
• Mark Bohr · Beaverton, US

Key dates

• Filing date: May 17, 2004
• Grant date: Sep 26, 2006
• Expiry date: Jul 20, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer layer.